1. Field of the Invention
The present invention relates to a multiphase DC/DC converter.
2. Description of Related Art
Conventionally, a multiphase DC/DC converter is known, in which a plurality of DC/DC converter circuits that are connected in parallel with each other are driven with the output phases deviated from each other and each output is summed up, so that a desired output voltage is generated from an input voltage.
As examples of conventional art related to the above description, there are JP-A-2003-284333 and JP-A-2007-116834 (hereinafter, called patent documents 1 and 2).
Indeed, the above conventional multiphase DC/DC converter is able to output a large electric current to a load compared with a single-phase DC/DC converter; accordingly, it is possible to preferably use the above conventional multiphase DC/DC converter as a power supply for loads (a CPU [Central Processing Unit] and the like) which have a large consumed electric current.
However, as for the multiphase DC/DC converter, there are many issues such as improvement in transient response characteristic, appropriate overvoltage protection operation, stabilization of drive frequency and the like which are to be studied to achieve further improvement in performance. Hereinafter, specific description is performed.
(First Background Art)
FIG. 5 is a circuit block diagram showing a first conventional example of a multiphase DC/DC converter. As shown in the drawing, the multiphase DC/DC converter as the first conventional example is so structured as to include: a plurality of DC/DC converter circuits 100-1 to 100-m (here, m≧2) which are connected in parallel with each other; and a control circuit 200 which generates drive signals S1 to Sm so as to drive the DC/DC converter circuits 100-1 to 100-m with the output phases of the DC/DC converter circuits 100-1 to 100-m deviated from each other; wherein each output from of the DC/DC converter circuits 100-1 to 100-m is summed up, so that a desired output voltage Vout is generated from an input voltage Vin.
Besides, in the multiphase DC/DC converter as the first conventional example, the control circuit 200 is so structured as to include: a comparator 201 which compares the output voltage Vout and a predetermined reference voltage Vref and outputs a comparison signal; a pulse signal generation portion 202 which by using the comparison signal as a trigger, generates a pulse signal S0 that has a predetermined pulse width; and a pulse distribution portion 203 which successively distributes pulses of the pulse signal S0 to generate the drive signals S1 to Sm; wherein the DC/DC converter circuits 100-1 to 100-m are each driven in an on-time fixed mode.
However, in the multiphase DC/DC converter as the first conventional example, in driving each of the DC/DC converter circuits 100-1 to 100-m in the on-time fixed mode, it is impossible to drive the respective phases at the same time and the on duty of each phase is limited to 100/m (%) even at the utmost or smaller; accordingly, there is a problem that when a sharp increase in the output current Iout occurs, the output voltage Vout drops from a target value.
FIG. 6 is a timing chart to explain the problem with the first conventional example. In FIG. 6, a case of m=2 is described as an example for simple description.
(Second Background Art)
FIG. 10 is a circuit block diagram showing a second conventional example of the multiphase DC/DC converter. As shown in the drawing, the multiphase DC/DC converter as the second conventional example is so structured as to include: the plurality of DC/DC converter circuits 100-1 to 100-m (here, m≧2) which are connected in parallel with each other; and the control circuit 200 which generates the drive signals S1 to Sm so as to drive the DC/DC converter circuits 100-1 to 100-m with the output phases of the DC/DC converter circuits 100-1 to 100-m deviated from each other; wherein each output from of the DC/DC converter circuits 100-1 to 100-m is summed up, so that the desired output voltage Vout is generated from the input voltage Vin.
Besides, the control circuit 200 has a structure in which based on a phase control signal PHASE input from outside, the control circuit 200 is able to arbitrarily set the number x (here, 1≧x≧m) of drive phases, that is, the drive-phase number, of the DC/DC converter circuits 100-1 to 100-m. In a case where the drive-phase number x of the DC/DC converter circuits 100-1 to 100-m is set smaller than the maximum value, both transistors NHy and NLy of a DC/DC converter circuit 100-y (here, (x+1)≦y≦m) other than the DC/DC converter circuits having the drive phase are turned off and the output terminal is brought into a high-impedance state.
When an overvoltage in the output voltage Vout is detected by an overvoltage detection circuit 300, the control circuit 200 has a structure in which the control circuit 200 stops the switching operation of the transistors NHx, NLx of the DC/DC converter circuit 100-x having the drive phase and turns on the transistor NLx on a low side; thus, the output voltage Vout is pulled down to a ground potential. According to such structure, even when an overvoltage in the output voltage Vout is detected, it is possible to protect circuit elements and the load by performing the above overvoltage protection operation.
However, in the multiphase DC/DC converter as the second conventional example, in a case where the drive-phase number x of the DC/DC converter circuits 100-1 to 100-m is set smaller than the maximum value, the transistor NLy on the low side of the DC/DC converter circuit 100-y other than the DC/DC converter circuits having the drive phase is normally kept in an off state regardless of detection of an overvoltage in the output voltage Vout; accordingly, there is a problem that the speed at which the output voltage Vout is pulled down to a ground potential is slow compared with the time of all-phase driving.
FIG. 11 is a timing chart to explain the problem with the second conventional example and represents in order from the top: the output voltage Vout; an overvoltage detection signal OVP; a gate signal of the transistor NL1; a gate signal of the transistor NL2; and gate signals of the transistors NL3 to NLm. In FIG. 11, it is assumed that the drive-phase number x is set at 2.
As shown in FIG. 11, in the time of 2-phase driving, when an overvoltage in the output voltage Vout is detected, the switching operations of the DC/DC converters 100-1, 100-2 having the drive phase are stopped and the transistors NL1, NL2 on the low sides are turned on. On the other hand, in the DC/DC converters 100-3 to 100-m other than the DC/DC converters having the drive phase, the transistors NL3 to NLm on the low sides are normally kept in the off state regardless of occurrence of an overevoltage in the output voltage Vout.
Specifically, in the multiphase DC/DC converter as the second conventional example, because a discharge route via the transistors NL3 to NLm is never used, the speed at which the output voltage Vout is pulled down to the ground potential becomes slow compared with the time of the all-phase driving.
(Third Background Art)
FIG. 14 is a circuit block diagram showing a third conventional example of the multiphase DC/DC converter. As shown in the drawing, the multiphase DC/DC converter as the third conventional example is so structured as to include: the plurality of DC/DC converter circuits 100-1 to 100-m (here, m≧2) which are connected in parallel with each other; and the control circuit 200 which generates the drive signals S1 to Sm so as to drive the DC/DC converter circuits 100-1 to 100-m with the output phases of the DC/DC converter circuits 100-1 to 100-m deviated from each other; wherein each output from of the DC/DC converter circuits 100-1 to 100-m is summed up, so that the desired output voltage Vout is generated from the input voltage Vin.
Besides, the multiphase DC/DC converter as the third conventional example has a structure in which based on the phase control signal PHASE input from outside, the multiphase DC/DC converter is able to arbitrarily set the drive-phase number of the DC/DC converter circuits 100-1 to 100-m. 
However, in the multiphase DC/DC converter as the third conventional example, the frequencies of the drive signals S1 to Sm are normally fixed at constant values regardless of the drive-phase number of the DC/DC converter circuits 100-1 to 100-m. Accordingly, the drive frequency of the entire multiphase DC/DC converter dramatically changes in accordance with the drive-phase number of the DC/DC converter circuits 100-1 to 100-m, which makes it to difficult to take measurers against noise.
FIG. 15 is a timing chart to explain the problem with the third conventional example. In FIG. 15, for simple description, only comparison among the drive signal S1 in the time of the 1-phase driving, the drive signals S1, S2 and a sum signal S1+S2 (which corresponds to a drive signal in a case where a single DC/DC converter circuit is assumed) of the drive signals S1 and S2 is performed.
As shown in FIG. 15, when it is assumed that the drive signals S1, S2 have a period of T, and there is a phase difference of 180° (which is equivalent to T/2) between the drive signals S1 and S2 in the time of the 2-phase diving, it is understood that the drive frequency of the entire multiphase DC/DC converter dramatically changes from a frequency f=1/T (the frequency of the drive signal S1) to a frequency of 2×f (the frequency of the sum signal S1+S2) between the time of the 1-phase driving and the time of the 2-phase driving.